The invention relates to a method for forming vertical interconnects in high-density semiconductor devices. In general, as device densities increase, formation of vertical interconnects, or vias, becomes more difficult.
Conventional vertical interconnect formation involves etching a high-aspect ratio void in a dielectric material, then filling the void with a conductive material. As dimensions decrease, the etch required to create the void becomes more difficult to perform cleanly and completely. Stopping the etch at the right point can also present challenges. Often it becomes necessary for vertical interconnects to be formed that are larger than the minimum feature size.
The present inventor, in U.S. Pat. No. 6,004,874, “Method for Forming an Interconnect,” describes forming a blanket etch stop layer, patterning post vertical interconnects using materials that provide an imperfect etch stop, then patterning the etch stop layer into lines or wires in the context of traditional two-dimensional structures.
There is a need, therefore, for a method of vertical interconnect formation with an easily controllable etch that allows vertical interconnects to be created at approximately the minimum feature size. This technique proves particularly valuable in dense monolithic three dimensional memory arrays.